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Renesas Announces Development of SRAM Using 16 nm FinFET for Automotive

Published: Dec 19,2014

Renesas Electronics Corporation announced the development of a new circuit technology for automotive information SoCs at 16 nanometer (nm) and beyond. Using this new circuit technology, Renesas tested the prototype of an SRAM, at the 16 nm node as the cache memory for CPU and real-time image processing blocks in an SoC, and successfully confirmed that this SRAM operates at the high speed of 641 ps under the low-voltage condition of 0.7 V.

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The new FinFET adopts a finned structure, to suppress power consumption and increase performance. It is, however, difficult to optimize the circuit constants in these FinFETs, and the development of new circuit design technologies has become an issue.

To overcome this issue, Renesas has now developed a new circuit technology for FinFET devices to allow high-speed read and write operations to be performed in a stable manner even at low operating voltages.

The newly-developed assist circuit technology makes it possible to achieve both high speed and stable operation, which are expected to be problematic as device fabrication process feature sizes continue to shrink, and it will contribute significantly to performance improvements in real-time image processing that is required for the leading-edge driving support systems and automated driving systems of the future.

Renesas intends to contribute to the creation of a safe, secure, and pleasurable driving experience by adopting this newly-developed SRAM in Renesas' leading-edge SoC products using the 16 nm FinFET fabrication process and quickly providing these products to our customers.

Renesas Electronics presented the results of this research at the International Electron Devices Meeting 2014 (IEDM 2014), held from December 15 through December 17, in San Francisco, U.S.

Features :

- The word line overdrive method makes both high-speed read/write operations possible at low voltages

- High-reliability optimal designs that take the variations inherent in the FinFET device into account

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