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Andes’s RISC-V Processor Records a Rapid Growth of Design Wins in 2018

Published: Apr 08,2019

HSINCHU, Taiwan – Andes Technology announced it achieved a record number of design wins for its new family of RISC-V processors during 2018. These include the 32-bit N25F/A25 and 64-bit NX25F/AX25. This represents a dramatic growth in the number of licenses signed soon after introduction of the RISC-V cores.

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Adoption of the RISC-V architecture is rapidly accelerating in China, spreading throughout the Asia Pacific region, and sweeping the U.S. Over a third of the 21 licensee agreements were signed in China and another third in Taiwan with the rest in the U.S., Korea and Japan. The wins are going into a wide range of application. Nearly half of the sockets are in artificial intelligence designs, where RISC-V plays an important role. Other applications adopting RISC-V include block chain, communications, fingerprint recognition, FPGA, IoT, security applications, and solid state storage devices.

The rapid growth of RISC-V proves that increasing numbers of developers are adopting RISC-V architecture for their applications. Key to Andes successful lead in the RISC-V market was its rapid adoption of the RISC-V architecture.

“We are thrilled at the customer acceptance of our RISC-V product line,” declared Andes Technology President, Frankwell Jyh-Ming Lin.

“We joined the RISC-V Foundation as founding member because we were convinced of the commercial viability of the RISC-V CPU. In addition, the RISC-V architecture contains many of the fundamental elements already in our existing CPU IP product family. As a result, once the RISC-V foundation published the instruction set architecture (ISA), Andes was able to quickly develop our line of 32/64-bit RISC-V IP cores.”

Owning to Andes’ rich experience in providing CPU IP, Andes achieved competitive advantage by meeting customers’ needs for RISC-V processor cores. “The advantage our IP has over competitive offerings is its ability to use special extensions already in existing Andes’ CPU IP to improve performance, plus other features such as PowerBrake, to reduce peak CPU power consumption; StackSafe, to enhance system safety; and CoDense to reduce overall code size for a design.”

Andes RISC-V cores are based on AndesStar V5 architecture with single and double precision floating point support for high-precision data computations and MMU (Memory Management Unit) for Linux applications. In addition to the compactness, modularity and extensibility advantages of RISC-V ISA, Andes also provides customer-instruction extension capability to facilitate the design of Domain-Specific Architecture/Acceleration (DSA).

“Andes’ RISC-V solution provides the capability to add custom extensions using our powerful Andes Custom Extension (ACE) tool,” stated Andes CTO and Executive Vice President, Dr. Charlie Hong-Men Su.

“With ACE customers can add extensions specifically for their target applications to eliminate software bottlenecks and significantly improve runtime performance. While other CPU cores do not allow designers to add their own instructions to a CPU architecture, Andes provides COPILOT (Custom-OPtimized Instruction deveLOpment Tool) for ACE, which does the tedious but essential work needed to add a new instruction to a CPU ISA: creates the instruction’s RTL, its instruction set simulator, and its tool extensions—compiler, assembler, and debugger—automatically.”

As the recent popularity of RISC-V is rising among the CPU IP industry especially in China, the growth of RISC-V adoption and ecosystem is expected to rapidly accelerate.

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