Taipei, Sunday, Jul 21, 2019, 06:31

News

Andes Launches First DSP Instruction Set for RISC-V Multi-Core Processors to Challenge the HPC Marke

By Korbin Lan
Published: Apr 22,2019

TAIPEI, Taiwan - Leading up to the RIC-V forum, RISC-V CON, which will be held in Hsinchu on May 9, Andes Technology Corporation on April 19 hosted an explanatory press conference for new processor products and ecosystem services. Their new products will include the first RISC-V processor of its kind with a DSP instruction set (A25MP/AX25MP), which can provide more than twice the operating performance of their competitors, and it is a computational tool for handling artificial intelligence applications.

More on This

Andes’s RISC-V Processor Records a Rapid Growth of Design Wins in 2018

HSINCHU, Taiwan – Andes Technology announced it achieved a record number of design wins for its new family of RISC-V processors during 2018...

Andes and SEGGER Partner to Deliver Professional Development Solutions for RISC-V

HSIN, Taiwan - Andes Technology announced the availability of SEGGER powerful development solutions support for Andes RISC-V processor families...

Andes Technology President Frankwell Jyh-Ming Lin stated that RISC-V architecture is equipped with command streamlining, which has the advantages of being modular and expandable, considerably facilitating development and ease of deployment. Furthermore, because RISC-V is an open source directive, developers are permitted to add to or modify it in accordance with their own requirements. Therefore, it has better design flexibility and will consequently gradually be favored by developers.

On the other hand, owing to the rise of AI and IoT trends, uniform specifications will no longer be pursued in product development, and more customization and differentiation will instead be sought out. As a result, this will motivate designers to move to more flexible RISC-V architectures and bring about an RISC-V boom.

President Lin elaborated, saying that Andes Custom Extension (ACE) tools will enable capable developers to quickly add tools for customized instructions into Andes’ processors, and they will be a major weapon in attracting customers to choose Andes’ processors.

Andes Technology CTO and Senior Vice President of Sales Charlie Hong-Men Su stated that A25MP and AX25MP are Andes’ first types of commercial RISC-V architecture multi-core processors which are equipped with complete DSP instruction sets. The A25MP is 32-bit, whereas the AX25MP is 64-bit, and both types can support up to four CPUs. Moreover, they have the capacity to reach 1.2GHz in 28nm manufacturing processes.

Dr. Charlie Su also stated that they were equipped with DSP instructions in response to customers’ requirements. In the past numerous customers expressed hopes that Andes’ cores could be equipped with DSP functionality; therefore, Andes adapted to the needs of their customers and launched DSP instruction sets as well as support for P-extension specifications.

(TR/ Phil Sweeney)

CTIMES loves to interact with the global technology related companies and individuals, you can deliver your products information or share industrial intelligence. Please email us to en@ctimes.com.tw

1041 viewed

comments powered by Disqus