Leveraging GUC's back-end design service expertise, the companies are working together to integrate Credo's 28G and 56G SerDes IP and have already taped out a solution based on TSMC's 16-nm FF+ process technology.

“Our collaboration with Credo is an extremely unique approach to solving some of the complex problems associated with designing high-performance devices at advanced technology nodes,” said Jim Lai, president of GUC. In other words, this is a model that will set a new standard for the entire semiconductor industry.

By working together at such an advanced node, the companies expect to significantly improve chip integration, shorten the design cycle and reduce power consumption in networking chips that are the backbone of switches, routers, and other network hardware.

Bill Brennan, President and CEO of Credo, said that working closely with GUC to ensure the seamless integration of our 28G and 56G IP with their 16nmFF+ SOC integration platform will lead to first-pass silicon success for their customers and accelerate the adoption of 16FF+ ASICs for the 100G and 400G enterprise networking and data center markets.

Networking devices have traditionally relied on wide channel counts to achieve the required bandwidth and system throughput due to the lack of availability of lower power, high performance SerDes at advanced processing nodes.

As one of the first companies to deliver a 56G SerDes IP solution, Credo offers technology that will significantly reduce the number of channels, chip area, and power consumption. The approach eliminates bottlenecks that can occur when multiple channels are used to increase the throughput and bandwidth of networking chips and systems.