The combined USB 3.1 IP is compliant with both USB 3.1 and USB 2.0/1.1 specifications. The IP supports all USB bus speeds: Super Speed Plus (10 Gbps), Super Speed (5 Gbps), High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps). It is compliant with Battery Charging Specification Revision 1.2, and is based on the eXtensible Host Controller Interface for the Universal Serial Bus (xHCI) Specification as Host Controller Interface.

The USB3.1 PHY/Controller is available now and is silicon proven on TSMC 16FF+ process technology. It supports USB protocols and is ready for USB Type-C connector. Ultra low-power consumption and robust transceiver performance makes it ideal for consumer applications including mobile, laptops and tablets.

"The 24/7 connected world poses numerous engineering challenges that can best be met through a customized, collaborative approach. Our collaboration to develop the next generation SoC IP is an example of how ASIC's will play an increasingly important role in technology advancement," explained Jim Lai, President GUC.