Leveraging its robust chip-package-PCB co-design capability, Faraday can provide customers with the system-level electrostatic design guidance of PCB layout to avoid potential system-level ESD design weakness; meanwhile, the essential analysis for system-level ESD-induced signal noise can be performed to determine the best design solution. In addition, Faraday’s reliability lab offers “one-stop system-level ESD test service” to meet customers’ system-level electrostatic related evaluation and test needs.

“Faraday not only provides common chip-level ESD protection service, but also offers the system-level service that further helps customers eliminate system-level electrostatic problems and achieve a smooth path to mass production,” said Jim Wang, vice president of operations at Faraday. “With our innovative ASIC expertise, we continue to work with our customers to provide the most efficient solutions to meet the growing demand for quality, enabling customers to seize market opportunities.”