Faraday's Gigabit Ethernet PHY (GPHY) is built upon a DSP-based transceiver architecture to optimize power, performance and area tradeoffs for highly integrated SoCs. To address the wired communication network connectivity, this GPHY offers superior performance of immunity to noise and inter-symbol interference for both single-port and multi-port networking applications, such as set-top box (STB), IP camera, network switch, and smart home gateway.

“By utilizing this GPHY solution, Faraday has helped customer’s ASIC project succeed in mass production for the multi-port networking application,” said Jason Lu, senior associate vice president of R&D at Faraday. “Through the experience, we ensure that IP customers can easily integrate this Ethernet PHY into their design and put more focus on their product developments on UMC’s 40LP platform.”

“UMC’s 40LP platform targets high-speed interface applications that also have power optimization requirements,” said T.H. Lin, director of IP Development and Design Support at UMC. “With Faraday’s newly-added Gigabit Ethernet PHY IP, customers can now explore more opportunities for networking solutions on our 40LP process technology with efficient and cost-effective advantages.”

In addition to 40LP, Faraday’s Gigabit Ethernet PHY is also being developed for UMC’s 28nm process technology.