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Astera Labs Expands Focus to Deliver Purpose-Built Solutions Addressing Connectivity Bottlenecks

Published: Mar 14,2021

Astera Labs announces its expanded focus to address system-wide performance bottlenecks in data-centric applications. The new Aries Compute Express Link (CXL 2.0) Smart Retimer portfolio (PT5161LX, PT5081LX) for low-latency connectivity is the first solution representing the company’s expanded mission and is actively being sampled to strategic customers.

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“With our expansion into the CXL ecosystem, Astera Labs is taking another giant leap to provide purpose-built solutions that unlock complex heterogeneous compute and composable disaggregation system topologies,” said Jitendra Mohan, CEO, Astera Labs. “The Aries CXL Smart Retimer portfolio builds upon our established industry leadership in PCI Express (PCIe) 4.0 and 5.0 interconnects and provides a seamless path to enable new workload-optimized platforms.”

The explosion of data and mainstreaming of specialized workloads - like Artificial Intelligence and Machine Learning - require purpose-built accelerators to work side-by-side with general-purpose CPUs on the same motherboard or within the same rack while sharing a common memory space. CXL 2.0 interconnect is key to enable such cache coherent system topologies.

“Astera Labs is following in the footsteps of our previous investments – Annapurna Labs and Habana Labs – to pioneer purpose-built solutions that truly transform the technology landscape,” said Avigdor Willenz, Astera Labs’ Founding Investor. “I believe Astera Labs’ latest CXL and PCIe connectivity solutions are fundamental to realizing the full potential of Artificial Intelligence in the Cloud.”

“As an early CXL Consortium member, Astera Labs contributed its connectivity expertise to the advancement of the CXL standard,” said Barry McAuliffe, CXL Consortium President. “It is great to see its first CXL silicon implementation come to market in support of a fast-growing CXL ecosystem.”

Astera Labs also announces availability of a new Low Latency Mode in Aries Smart Retimer portfolio for PCIe connectivity with Intel Xeon Scalable processors. This development was the result of close collaboration with Intel Corporation to further reduce latency in PCIe links to sub-10ns and enhance performance in data-centric workloads. Astera Labs is the first vendor to demonstrate robust PCIe 5.0 interoperability with Intel Xeon Scalable processors code-named ‘Sapphire Rapids.’

Furthermore, Astera Labs announces its Equinox product – the new plug-and-play Smart Retimer Add-in-Card for PCIe/CXL applications. Developed in partnership with Intel Corporation, the Equinox Add-in-Card and associated purpose-built firmware will simplify development of PCIe 5.0 enabled systems with Intel’s latest Xeon Scalable processors. This represents Astera Labs’ transition to offer easy-to-use, plug-and-play boards to rapidly implement complex system topologies.

“PCIe Gen5 and CXL are foundational technologies to heterogeneous compute workloads and data center architectures today and tomorrow,” said Zane Ball, Corporate VP and General Manager Datacenter Engineering and Architecture at Intel Corporation. “Intel is collaborating with ecosystem leaders like Astera Labs to significantly reduce PCIe and CXL interconnect latency on upcoming Intel Xeon Scalable platform code-named ‘Sapphire Rapids’ and additional platforms.”

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