With a single, multi-protocol IP, designers can easily address changing memory and system cost requirements in consumer, mobile and enterprise applications. They can select the optimal DRAM subsystem implementation for their specific application after the SoC has already been designed.

DDR4 is primarily used in enterprise applications requiring high-capacity and high-reliability DRAM subsystems. LPDDR4 meets the power/performance requirements of mobile applications.

Consumer applications, on the other hand, have traditionally used DDR3 DRAMs, moving to DDR4 to benefit from DRAM commodity pricing. Over time, performance requirements for these application areas are currently expected to grow, while performance levels for LPDDR4 are expected to improve. With the new IP, designers can easily migrate from DDR4 to LPDDR4 without a chip redesign.

“The Cadence DDR PHY IP offers high performance, high configurability and flexibility critical to our networking SoC designs,” said Gaurav Singh, vice president technical strategy at Applied Micro Circuits Corporation.

“With access to the next-generation protocol and having additional flexibility between DDR and LPDDR, Cadence is allowing us to further innovate and provide greater differentiation and value to our customers.”

“For the first time, high performance mobile, consumer and enterprise application requirements can be addressed in a single DDR IP solution,” said Martin Lund, senior vice president of the IP Group at Cadence.

“By using the Cadence multi-protocol DDR IP, we believe our customers can have more confidence that their products can meet memory subsystem requirements, allowing them to optimize for performance, power and density in their end system.”