Cadence Design Systems announced the new Cadence Tensilica Vision P5 digital signal processor (DSP), its flagship high-performance vision/imaging DSP core. This imaging and vision DSP core offers up to 13X performance boost, with an average of 5X less energy usage on vision tasks compared to the previous generation IVP-EP imaging and video DSP.
The Tensilica Vision P5 DSP is built from the ground up for applications requiring ultra-high memory and operation parallelism to support complex vision processing at high resolution and high frame rates. As such, it is ideal for off-loading vision and imaging functions from the main CPU to increase throughput and reduce power. End-user applications that can benefit from the DSP’s capabilities include image and video enhancement, stereo and 3D imaging, depth map processing, robotic vision, face detection and authentication, augmented reality, object tracking, object avoidance and advanced noise reduction.
The Tensilica Vision P5 DSP core includes a significantly expanded and optimized Instruction Set Architecture (ISA) targeting mobile, automotive advanced driver assistance systems (or ADAS, which includes pedestrian detection, traffic sign recognition, lane tracking, adaptive cruise control, and accident avoidance) and Internet of Things (IoT) vision systems.
The advances in the Tensilica Vision P5 DSP further improve the ease of software development and porting, with comprehensive support for integer, fixed-point and floating-point data types and an advanced toolchain with a proven, auto-vectorizing C compiler. The software environment also features complete support of standard OpenCV and OpenVX libraries for fast, high-level migration of existing imaging/vision applications with over 800 library functions.
Features:
－ Wide 1024-bit memory interface with SuperGather technology for maximum performance on the complex data patterns of vision processing
－ Up to 4 vector ALU operations per cycle, each with up to 64-way data parallelism
－ Up to 5 instructions issued per cycle from 128-bit wide instruction delivering increased operation parallelism
－ Enhanced 8-,16- and 32-bit ISA tuned for vision/imaging applications
－ Optional 16-way IEEE single-precision vector floating-point processing unit delivering a massive 32GFLOPs at 1GHz
