Synopsys today announced availability of its new ASIP Designer tool that speeds the design of application-specific instruction-set processors (ASIPs) and programmable accelerators.
ASIP Designer's language-based approach allows the automatic generation of synthesizable RTL and software development kits (SDKs) from a single input specification, accelerating the processor design and verification effort by up to 5X compared to traditional manual approaches. ASIPs are deployed in a wide range of signal-processing intensive applications, including wireless base stations, mobile handsets, audio processing, image processing and cloud computing.
ASIP Designer enables users to explore multiple processor architecture alternatives in minutes. Using a single input specification in the nML language, the tool automatically generates both the synthesizable RTL of the processor as well as an SDK that includes an optimizing C/C++ compiler, instruction set simulator, linker, assembler, software debugger and profiler. This ensures consistency of the hardware and the SDK at all stages of the design process.
The patented compiler generation technology includes an LLVM compiler front-end and support for the OpenCL kernel language. Immediate availability of the compiler enables users to run their C, C++ and OpenCL application code on the automatically-generated instruction-set simulator as soon as the nML-based description is available. With this unique "compiler-in the-loop" approach as well as the extensive profiling capabilities of the debugger, ASIP Designer users can rapidly analyze and explore ASIP architectures and instruction sets to find the optimal power and performance design points for the target application.
ASIP Designer also automatically generates a SystemC-based transaction-level model, allowing pre-silicon software development using virtual prototypes such as those designed with Synopsys' Virtualizer tool set. A common and easy-to-use flow from RTL generation to instantiation in the HAPS FPGA-based prototyping system, in addition to the automatic generation of JTAG-based on-chip debug logic, enables designers to integrate the ASIP into the system-on-chip (SoC) design and connect the prototype with real-world I/Os to validate the hardware-software integration.
A wide range of example ASIP designs for highly differentiated architectures, provided in nML source code, allows designers to quickly start designing their own ASIP that targets their specific application requirements.
