Spansion Inc. announced Spansion HyperBus Interface, a breakthrough that dramatically improves read performance while reducing the number of pins. The Spansion HyperBus Interface is being implemented broadly by leading system-on-chip (SoC) manufacturers.
Spansion is also introducing today the first family of products based on this new interface, Spansion HyperFlash NOR Memory devices, with read throughput of up to 333 megabytes per second—more than five times faster than ordinary Quad SPI flash currently available with one-third the number of pins of parallel NOR flash.
Embedded design engineers need high-speed solutions to address the instant-on and interactive graphical user interface (GUI) requirements of next-generation electronics. The Spansion HyperBus Interface will enable a wide range of high-performance applications, such as automotive instrument clusters, infotainment / navigation systems, advanced driver assistance systems (ADAS), hand-held displays, digital cameras, projectors, factory automation, medical diagnostic equipment, and home automation appliances.
The efficient 12-pin Spansion HyperBus Interface consists of an 8-pin address/data bus, a differential clock (2 signals), one Chip Select and a Read Data Strobe for the controller, reducing the overall cost of the system.
Features：
- read throughput of up to 333 megabytes per second
- enable a wide range of high-performance applications
- consists of an 8-pin address/data bus
- a differential clock (2 signals)
- one Chip Select
- a Read Data Strobe for the controller
