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Such systems typically call for a complex timing architecture that incorporates multiple reference clocks capable of coordinating the various devices and satisfying the exact clock frequency, voltage level and jitter specifications of interfaces such as PCI Express, Gigabit or 10 Gigabit Ethernet, USB3.0 and others.
Engineers must arrange multiple discrete clock signals to satisfy the timing needs of all devices in the system. The resulting timing architecture can include multiple crystal oscillators, clock generator ICs and multiplexers, which can occupy a large PCB area and add to bill of materials costs. Purchasing overheads and procurement risks are also greater when a large number of discrete components need to be managed.
In addition, some applications may require extra frequency-margined clock references operating at above or below nominal frequency, which allow tests to verify the effects of temperature or age-related frequency drift as well as system margining. Adding one or more frequency-margined timing networks for test purposes further exacerbates the challenge designers face to minimize solution size, cost, and procurement and assembly issues.
Consolidating Clock Sources
Demands to simplify the complexity and to lower size and cost overheads associated with the timing architecture are driving innovative new integrated timing devices. These are capable of providing multiple programmable clock sources that offer greater design flexibility while also meeting very tight specifications on jitter.
The IDT VersaClock 5 family of fully programmable multi-output clock generators is an example of this type of device, and is packaged as a compact 4mm x 4mm 24-pin VFQFPN Very-thin Fine-pitch Quad Flat Pack device.
This new generation of clock generators differs from conventional integer-N phase-locked loop devices that provide multiple clock outputs at integer multiples of the reference input. A VersaClock 5 can produce output clock signals at any multiple of the input reference, and with its fractional output dividers is not restricted to pure integer multiples.
In addition, each clock channel can be configured independently as dual LVCMOS outputs, or as LVPECL or LVDS outputs or the Host Clock Signal Level (HCSL) protocol as specified for PCI Express cards. The flexibility to configure clock-output channels independently, in accordance with any of these specifications, can eliminate the need for discrete level translation ICs in a large number of applications.
The first device in this family integrates a single PLL and four Fractional Output Dividers (FODs) generating four pairs of clock outputs (figure 1). These can be used as four differential or eight single-ended outputs, and can be individually configured for any frequency from 5MHz to 350MHz.
This frequency range encompasses the clock requirements for state-of-the-art, high-speed interconnect specifications such as Gigabit Ethernet (125MHz), 10-Gigabit Ethernet (156.25MHz), and PCI Express (100MHz/120MHz), as illustrated in figure 2. Other standards such as Fibre Channel (106.25MHz), XAUI (125MHz), and SONET OC-48 (155.52MHz) can also be supported.
@內文:Since only one crystal oscillator is required as a reference, using this type of device greatly reduces the number of individual crystal oscillators required to fulfill all system timing requirements. This not only reduces component costs and saves PCB real-estate, but also simplifies design for electromagnetic compatibility (EMC) by eliminating multiple high-frequency sources. In addition, one pin of the VersaClock® IC is dedicated to providing a buffered version of the reference source, which can save the need for a further crystal in some applications.
In addition to saving component count and BOM costs, using an integrated multi-channel timing IC can also greatly reduce procurement risks since purchasers only need to manage the availability of one crystal part number to ensure that production can continue without delays.
Designers can save board space with lower power consumption by using a single integrated device to generate multiple clock references as compared to multiple discrete components. On top of this saving, the VersaClock® 5 family incorporates low-power chip design techniques to reduce the core power consumption to less than 100mW, or 300mW with all outputs operational. This is significantly less than the power consumed by competing multi-channel clock ICs. The effect of reducing overall system power helps to simplify power supply design, ease thermal constraints and maximise battery life.
Minimising RMS Jitter
The jitter performance of programmable clock generator ICs has been improving steadily through successive generations, to meet the demands of high-speed connectivity standards. VersaClock 5 devices have RMS phase jitter of less than 0.7 picoseconds over the full 12 kHz to 20 MHz integration range.
High-speed interconnect standards such as 1G or 10G Ethernet and PCI Express Gen 3 specify a maximum jitter budget taking into account the contributions of all jitter sources. These include not only the clock, but also the transmitter as well as the effects of terminations and board traces. The RMS jitter budget for a 10G Ethernet connection can be as low as 1.55ps (10G BASE-R), while PCI Express Gen 3 specifies RMS jitter budget of 3.0ps for the link.
Minimising the RMS phase jitter contributed by the clock source gives the designer a greater margin to meet the link jitter budget when other contributions are taken into account. By contributing less than 0.7ps RMS phase jitter, VersaClock technology allows a large jitter margin when working with these and other high-speed interconnects such as SONET, Fibre Channel and XAUI.
Configuration and In-System Programming
Some applications may require a convenient integrated clock tree that can be connected in-circuit and will power up directly in the desired configuration. The VersaClock IC has four One-Time Programmable (OTP) Memory banks, which allow the device to operate in this way. The user can program the OTP memory using IDT’s Timing Commander software.
The Windows-based Timing Commander platform supports product-specific personality files that provide a convenient user interface that helps configure the VersaClock 5 device (figure 3). Schematic and bit-set views are available, which allow easy adjustment of settings such as input and output frequencies.
A register view is also available, which gives control over individual register bit settings. By hovering over a specific setting or functional block, the user can call up detailed information and design tips that save referring to the device datasheet. Timing Commander also verifies the selected settings, and informs the user of any problems such as illegal or incompatible selections.
Alternatively, VersaClock devices can be pre-programmed at the factory, and supplied as turnkey components ready to be soldered down onto the customer’s PCB. The device will perform as required on power up.
The four OTP banks enable VersaClock devices to store multiple alternative configurations. This allows engineers to use one part number in multiple projects, which can simplify procurement and inventory management. The ability to store up to four configurations also caters to applications that require frequency margining.
Up to three programmable sub-configurations can be stored, in addition to the nominal settings, which can be used to perform margin testing, and so verify worst-case system behaviour without requiring additional circuitry. The desired configuration is selected via the device’s I2C interface. The internal OTP memory is also in-system programmable via the I2C interface, which can save any need to pre-program devices using an external programmer.
The latest generations of fully programmable multi-output clock ICs meet demands to simplify timing architecture design, save precious PCB space and overcome procurement challenges. Judicious selection of devices that offer best-in-class performance [also delivers opportunities to benefit from] significant power savings and a larger jitter margin when designing state-of-the-art high-speed data interfaces.