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Magnetic Testing for STT-MRAM Enabling Yield Management in Volume Manufacturing

By Siamak Salimy
Published: Jun 02,2021

Because STT-MRAM (Magnetic Random-Access Memory) is fast, non-volatile, durable, low power and scalable, it is one of the new memory technologies fast gaining traction today. It is a strong candidate to replace eFlash, and is especially attractive for automotive, IoT and other low-power applications. However, to support the high yields needed for volume manufacturing, it requires new approaches to testing.


STT-MRAM technology is a resistive memory where information (bit) is stored thanks to the magnetic state of the device. It is based on Magnetic Tunnel Junction (MTJ), the fundamental spintronic device associating non-volatility, high-speed, reliability, scalability, and low power consumption at the same time. The MTJ is integrated in the interconnects levels of a CMOS manufacturing process. It is structured like a sandwich, with two ferromagnetic layers called the Free layer (FL) and Reference Layer (RL) separated by a thin insulator acting as a tunnel barrier.


The device has a low-resistance state when the magnetizations of FL and RL are parallel (P) and a high-resistance when anti-parallel (AP). In chip operation, STT-MRAM is programmed electrically like transistor-based memory technologies. However, because of the magnetic nature of information stored in STT-MRAM, several new electrical tests require the application of an external magnetic field during the STT-MRAM chip fabrication process. These tests aim at extracting physical parameters, accelerating testing speed and evaluating magnetic immunity.



Figure 1
Figure 1

Fundamental parameters of STT-MRAM

STT-MRAM has two states of resistances (P and AP) and the ratio between the two states is defined as the Tunnel Magneto Resistance (TMR) where RAP and RP are the resistances in AP and P states, respectively (1).



Figure 2
Figure 2

To switch from P to AP states, a minimum of current is required to exceed the energy barrier EB between the two states. EB is dependent on manufacturing process-related parameters and is key in the retention time performance of the memory point through the thermal stability factor.



Figure 3
Figure 3

Where kB is Boltzmann constant, T is the temperature, and t0 is the inverse attempt frequency. Higher ∆ results in a more stable magnetic state of the MTJ and consequently requires more energy to be programmed. The thermal stability factor can be optimized to the targeted application. For example, the data retention time requirement for working memory applications primarily demands scalability (high-density integration) and speed of operation. On the other hand, for automotive or industrial storage memory, the primary concern is robust storing capacities in harsh environments.


TMR, switching ability and stability factors of STT-MRAM MTJs are extracted through the hysteresis curve of the MTJ measured by varying an external magnetic field perpendicular to the device surface (parallel to the FL and RL) while sensing the MTJ resistance.



Figure 4
Figure 4

MRAM Device Level Test Requirements in manufacturing process

In CMOS or FD-SOI technologies integrating STT-MRAM, the MTJ full stack is finalized at the end of the wafer fab process (front-end).



Figure 5
Figure 5

The first step of device level testing is at the WAT (Wafer Acceptance Test) to control the manufacturing process through specified parameters such as Rp, Rap, TMR and ∆ as well as several others including breakdown voltage. At this step, MTJ test structures representative of those in the STT-MRAM chip are used as test vehicles to extract the hysteresis curve through magnetic and electrical excitations. In this test the STT-MRAM wafer is sorted. The key factor to achieving competitive testing time in WAT is fast variation of the magnetic field on top of the device in order to measure the hysteresis curves in the shortest time.


In the back-end process, the chip on wafer must be tested for wafer yield management. This is done at the Wafer Sort (WS) test aiming at binning the chip before the assembly process. In Final Test (FT), singularized packaged chips are tested to manage product manufacturing yields.


WS tests evaluate the functionality of the embedded logic memory. The programming and reading of each bit in the memory array is cycled. Bits in permanent switching faults that originated in fabrication process issues are identified for classification purposes. Non-persistent switching faults, which are due to the stochastic nature of spin-transfer torque switching in STT-MRAM, are quantified to validate that occurrences do not exceed the ppm range.


Extraction of the retention time of each bit in an STT-MRAM array is also mandatory. For some applications, like automotive or storage class memories, long (+10 years) retention time is required, which is exceedingly long to test. To compress testing time of retention tests, acceleration factors such as temperature, disturb current and external magnetic field are of great interest.


FT is complementary to WS with the addition of magnetic immunity test, which involves the application of an external field to disturb the chip. While the field is varied, memory reading is looped to validate that stored information is not affected by parasitic fields of strength lower than the range of the specified level of immunity.


Hprobe develops magnetic automated test equipment dedicated to testing MRAM under the application of an external field. Hprobe magnetic testers are designed specifically for WAT, WS and FT control steps and embed state-of-the-art efficient and cost-competitive test methods for STT-MRAM.


(Siamak Salimy, Founder and CTO of Hprobe)


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