Faraday’s 22ULP/ULL fundamental IP is designed with enhanced routing, as well as optimal power, performance and area (PPA) to address low-power SoC requirements. Compared to 28nm capabilities, the 22nm cell library can reduce chip die area by 10% or decrease power consumption by more than 30% under the same performance rate.

In addition, the standard cell libraries can work under a wide voltage range from 0.6V to 1.0V and support always-on components in SoC with ultra-low leakage; the versatile IO libraries include generic IO, multi-Vt IO, RTC IO, OSC IO, and analog ESD IO; the memory compilers feature dual power rail function, multiple power-saving modes, and read/write assist function.

C.H. Chien, associate vice president of R&D at Faraday, said, “With our long-term collaboration with UMC and extensive ASIC experience, we are able to provide professional services for IP adoption on UMC’s process technologies. By leveraging UMC’s 22nm technology, our newly-launched logic library and memory compiler IP can facilitate customers to develop lower-power SoC targeted to IoT, AI, data communication, multimedia, and other emerging applications with cost advantages and faster time-to-market.”

T.H. Lin, director of IP Development and Design Support division at UMC, said, “SoC designers require energy-efficient solutions for diversified applications. With the availability of Faraday’s fundamental IP on our production-ready 22nm specialty process, customers now have access to comprehensive design support resources on our competitive 22nm platform that includes 22ULP and 22ULL options to target a wide variety of applications.”