The PCI Express 4.0 specification, the next generation of the PCI Express I/O standard, doubles throughput to 16 GT/s and is currently at a preliminary revision 0.3 within the PCI Special Interest Group (PCI-SIG).

The DesignWare IP for PCI Express 4.0 architecture enables easy system-on-chip (SoC) integration of 16 GT/s performance and the power-saving features defined in the PCI Express 4.0 specification. Based on proven technology in the DesignWare IP for PCI Express 3.0, 2.1 and 1.1 architectures, which combined have more than 1,000 design wins, the DesignWare IP for PCI Express 4.0 architecture allows designers to quickly incorporate the new PCI Express 4.0 standard into their products with less risk and improved time-to-market.

The DesignWare PHY IP for PCI Express 4.0 architecture will support full-featured bifurcation and aggregation, offering designers the flexibility either to configure the PHY macro into multiple individual links at 2.5, 5, 8 or 16 GT/s, or to aggregate the PHY macro up to 16 lanes.

For increased signal integrity at high-speed data rates across legacy channels, the PHY analog front-end will include 5-tap DFE, continuous time linear equalization (CTLE) and feed forward equalization (FFE) with advanced algorithms for link initialization and adaptation.

As power reduction is a key requirement in many markets, the DesignWare PHY IP will reduce both active and standby power consumption through advanced techniques including L1 sub-states. Support for Separate Refclk Independent SSC (SRIS) will allow the use of cables to enable a new class of PCI Express applications outside of the system.

The low-power, low-latency DesignWare Controller IP for PCI Express 4.0 architecture is backward compatible with the PCI Express specification (4.0, 3.0, 2.1, 1.1, M PCIe and optional features including L1 sub-states) across Switch, Endpoint, Dual Mode and Root Complex port types, with support for embedded DMA and SR-IOV. ARM AMBA 4 AXI, AMBA 3 AXI and AMBA AHB and native interfaces are available in the DesignWare Controller IP for PCI Express 4.0 architecture, as well as in previous generations, enabling designers to quickly upgrade to the PCI Express 4.0 technology.

Based on existing DesignWare IP architectures, the DesignWare Controller IP for PCI Express 4.0 architecture supports multiple lanes (x1 to x16) and multiple datapath widths, enabling an optimized solution for the target application while minimizing gate counts and reducing design risk.