Quartus II software version 14.0 allows users to be more productive and achieve the fastest FPGA and SoC design closure in the industry. The latest release includes a rapid recompile feature that reduces compile times by up to 4X when making small design changes and a best-in-class PCI Express (PCIe) IP solution that delivers enterprise-class performance. In addition, this release offers expanded AXI support in the Qsys system integration tool and a rapid prototyping design flow in the Altera SDK for OpenCL.

A re-architected rapid recompile feature allows users to make small changes to their design and recompile in a fraction of the time versus doing a full compile. Using rapid recompile, designers will experience a speed up of up to 3X for pre-synthesis HDL changes and up to 4X for post-fit SignalTap II logic analyzer modifications, while preserving placement and routing for the unchanged portion of the design. Rapid recompile now supports all 28 nm Cyclone V, Arria V and Stratix V FPGAs.

Altera continues to bolster its best-in-class IP portfolio with the FPGA industry’s highest performance PCIe solution. Altera’s best-in-class PCIe solution boosts application performance by delivering up to 6.7 GB/s throughput and greater than 400K input/output operations per second (IOPS). The solution includes a newly architected DMA engine, enterprise-ready device drivers and reference designs that greatly simplify the evaluation and design integration process.

Enhancements to the Qsys system integration tool simplify the process of connecting system-level hardware components. Qsys expands its support for the AMBA AXI3 and AXI4 specification to include support for AXI4-Lite, a light-weight version of AXI4, and AXI4-Stream, for point to point connections. These enhancements enable better design reuse by supporting a broader range of custom IP and easing integration with Altera and third-party developed IP.

For software programmers targeting FPGAs, Altera also released today updates to the Altera SDK for OpenCL version 14.0. This latest release includes a rapid prototyping design flow that allows programmers to prototype designs on an FPGA accelerator board in minutes. Several reference platforms that further accelerate the FPGA development process are also included in the latest OpenCL release.