The wide array of IP for the 16FF+ process enables systems and semiconductor companies to take advantage of the 15 percent speed improvement with same total power or 30 percent total power reduction at the same speed compared to the16FF process.

Currently under development for the 16 FF+ process, the Cadence IP portfolio includes multiple high-speed protocols for several key memory, storage and interconnect standards critical in the development of advanced SoC designs.

Silicon-tested IP is expected to be available beginning in Q4 2014. For detailed protocol information and availability details, customers should contact their local Cadence salesperson.

“Our new 16nm FinFET Plus process is an important development for next-generation SoC designs as they balance the task of increasing performance while reducing power and area,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC.

“As a long time trusted TSMC partner, we believe Cadence will play a vital role in the broad adoption of this new process with its certified tools and IP portfolio.”

“Our broad portfolio of IP for 16 FinFET Plus will enable design teams to ramp quickly on next-generation SoC designs and immediately realize the performance and power benefits of this new FinFET process,” stated Martin Lund, senior vice president and general manager of the IP Group at Cadence.