Designed to meet the stringent specifications of the PCIe Generation 1/2/3 standards, the new Si50122 clock leverages Silicon Labs’ low-power PCIe and CMEMS technologies to provide an energy-friendly, crystal-less timing solution for a wide range of applications. The PCIe clock is ideal for digital video and still cameras, IP set-top boxes, HD streaming video players, high-definition digital TVs, home entertainment and audio systems, multi-function printers, consumer and small-business storage, and home gateway and wireless access equipment.

The Si50122 is the first clock generator to incorporate Silicon Labs’ patented CMEMS technology. The internal CMEMS resonator provides a stable frequency reference to the device’s CMOS clock circuitry, eliminating the need for a bulky, discrete quartz crystal.

By leveraging CMEMS technology, the Si50122 PCIe clock provides the benefits of shock and vibration immunity, exceptional reliability and guaranteed performance under harsh conditions such as extreme temperature swings. Because handheld consumer electronics products are susceptible to being bumped or dropped, using a robust CMEMS PCIe clock generator rather than a crystal-based solution eliminates the risk of system failure caused by a broken quartz resonator.

Offered in a tiny 2 mm x 2.5 mm 10-pin TDFN package, the Si50122 is the smallest PCIe clock generator available, as well as the industry’s lowest power crystal-less PCIe clocking solution. This industry-leading combination of small size and ultra-low power makes the Si50122 a best-in-class solution for space-constrained, handheld and battery-powered consumer and embedded applications that are adopting the PCIe interconnect standard.

To reduce system cost, power consumption and component count and to simplify board design, the Si50122 PCIe clock generator uses a low-power “push-pull” HCSL output buffer, which eliminates the need for all external termination resistors at the HCSL outputs.

Competing devices use a legacy output buffer architecture that requires up to four termination resistors per output and a current source resistor, forcing designers to manage up to nine external resistors for a two-output device.

By eliminating numerous external components, push-pull technology enables designers to create a continuous transmission line from the output pin to the receiver, resulting in cleaner signal integrity. Push-pull technology at the output buffer reduces power consumption by more than 60 percent compared to traditional constant-current technology used by almost all other PCIe clock suppliers.

The Si50122 PCIe clock provides two low-power 100 MHz differential HCSL outputs and one 25 MHz LVCMOS clock output. Since it is a crystal-less solution, it does not require an external 25 MHz frequency source.

As with Silicon Labs’ entire PCIe timing IC portfolio, the Si50122 device exceeds the jitter requirements for the PCIe Gen 1/2/3 standards and supports optional spread spectrum modulation for electromagnetic interference (EMI) reduction.