Complete with verification plans, built-in coverage and a protocol-aware memory debug environment, Verdi Protocol Analyzer, Synopsys VIP for LPDDR4 is a complete VIP solution that accelerates verification closure for designers of low power memory controllers and systems on chips (SoCs).

"LPDDR4 is an exciting step forward in technology providing lower power and higher performance, enabling the mobile industry to stay on the leading edge of the performance curve," said Kevin Widmer, vice president of technical marketing at SK hynix.

"The release of Synopsys memory VIP with advanced verification features devised for the LPDDR4 specification enables faster development of products and enables higher-confidence in compliance verification for SoCs and designs with memory interfaces."

Synopsys' 100 percent native SystemVerilog VIP for the JEDEC LPDDR4 memory protocol specification includes transactor and monitor functions to provide a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on LPDDR4-based designs. In addition to providing LPDDR protocol verification, the Synopsys LPDDR4 VIP can be dynamically configured to model any memory vendor component without the need to recompile, enabling SoC teams to rapidly verify the range of components that will be used with their SoCs.

"We have collaborated extensively with leading-edge SoC design teams to address the increasingly demanding process of protocol compliance for on-chip buses, off-chip interfaces and memory," said Debashis Chowdhury, vice president of R&D for the Synopsys Verification Group. "We continue to deliver solutions that enable designers to accelerate their SoC verification closure and decrease time to market. Synopsys LPDDR4 VIP provides SoC teams with the built-in protocol knowledge, features and methodology support to save time, increase design quality and meet project schedules."