With a capacity of 50 million equivalent ASIC gates and the industry's highest I/O count, the Virtex UltraScale VU440 FPGA leverages the UltraScale architecture's ASIC-like clocking, next-generation routing, and logic block enhancements to deliver best in class utilization, making it ideal for ASIC prototyping and large scale emulation.

"By being the first to receive samples of the Virtex UltraScale VU440 device, we are able to accelerate HAPS FPGA-based prototyping development to ensure the earliest availability of a complete solution for our customers," said John Koeter, vice president of marketing for IP and prototyping at Synopsys.

"The new UltraScale devices combined with HAPS' unique capabilities enable us to deploy our next-generation prototyping systems to satisfy our customers' requirements for higher capacity, increased performance and easier integration."

With the Virtex UltraScale VU440 FPGA, Xilinx continues to break through the limitations of Moore's Law with its second generation SSI-technology. Production qualified at the 28nm node, the SSI technology is built on TSMC's CoWoS (Chip-on-Wafer-on-Substrate) 3D IC process to achieve even greater silicon scaling, as well as power and performance benefits by integrating multiple components on a single device. Along with 5X more inter-die bandwidth and a unified clocking architecture across slice boundaries, UltraScale 3D IC devices deliver a virtual monolithic design experience for fast implementation and design closure.

"The VU440 is a powerful vehicle for prototyping any type of ARM®-based SoC prior to tapeout," said John Goodenough, vice president of engineering systems at ARM.

"The capacity and performance of this new FPGA from Xilinx enables multicore prototyping of even the most advanced ARMv8-A architectures, improving hardware and software development schedules, thereby enabling faster time to market for next-generation SoCs."