Prior to the Stratus platform, no high-level synthesis tool was robust enough to be used across an entire SoC design, and designers were forced to choose the parts of their designs in which they would utilize the technology.

“With our high-level synthesis flow and the Stratus platform, we're now doing the kinds of things that we couldn't have imagined doing previously,” said Ray McConnell, chief technology officer of Blu Wireless Technology.

“For example, we can now have a working prototype of a complete multi-gigabit modem with a mmwave beamsteering antenna available when we're doing the integration and system and software validation. Previously, we would have had to use poor approximations for early validation. Having an early working prototype is having a significant business impact in terms of our potential customers' enthusiasm and confidence."

“Delivering SoCs with unique IP, while meeting tight schedule windows and keeping development costs down, continues to be a growing customer challenge,” said Charlie Huang, executive vice president, Worldwide Field Operations and System and Verification Group at Cadence.

“The Stratus platform leverages the best of the Forte and Cadence technologies, making it the most broadly applicable and usable high-level synthesis tool on the market today.”

Features:

－ A sixth generation high-level synthesis core engine to provide excellent usability, scalability, and QoR across the full application space, including both control-centric and datapath-centric designs containing hundreds of blocks

－ Full integration with Cadence Encounter RTL Compiler and Cadence Encounter Conformal ECO Designer to allow physically-aware and ECO-aware high-level synthesis and minimize implementation changes from Engineering Change Orders

－ Rich intellectual property library of I/O interfaces and customizable floating point datatypes to increase productivity by giving designers synthesizable optimized SystemC building blocks

－ Full IDE and automation of tool flow and multiple scenario evaluation to enable full architectural exploration, and improve verification by providing a consistent environment from early TLM models through gates