The cores maximize processing throughput by retrieving instructions and data from memories that are tightly coupled to the processor pipeline, reducing the number of accesses to system memory along with the associated latency and power consumption penalties.

The ARC MetaWare Development Toolkit has been enhanced to offer full C/C++ programming support for the cores' DSP instructions and XY memory as well as a rich library of DSP functions to facilitate software development. The new cores are optimized for DSP-intensive functions such as sensor fusion, voice detection, speech recognition and audio processing that are common in Internet of Things (IoT) and other embedded applications.

The ARC EM9D and EM11D cores deliver the highest level of digital signal processing performance to date in the ARC EM DSP Processor family. All EM DSP cores implement a three-stage pipeline and are ideal for applications with a mixture of control and DSP workloads. The EM9D and EM11D take advantage of regular data access patterns common in signal processing code by integrating separate X and Y memories with hardware support for address generation and DMA to move data in and out of the memories. This enables a sustained throughput of one 32x32 MAC operation or two 16x16 MAC operations per clock cycle with minimal energy and area overhead.

These new processors have also been enhanced to support full integer, fractional divide and square root operations, unaligned loads/stores and bitstream parsing. These features enable the EM9D and EM11D to deliver the additional DSP performance required to execute complex sensor algorithms, as well as improve processing efficiency for a range of audio formats including MP3, SBC, OPUS and AAC LC. For example, the logic power consumption of the EM9D performing MP3 decode at 44.1 kHz, 128 kbps on a 28-nanometer process (nominal) is less than 40 microwatts.

The new EM9D and EM11D, like all ARC processor cores, are supported by the DesignWare ARC MetaWare Development Toolkit, a complete suite of tools for developing, debugging and optimizing software targeted for ARC processors. New features to ease DSP programmability and optimize applications for use with the XY memories have been added to the latest MetaWare release.

For regular C code, the compiler automatically generates ARCv2DSP ISA instructions to deliver better performance, including guided and auto vectorization optimizations. Programmers can also efficiently target the cores' DSP and XY memory resources directly through the use of C code with qualifiers and primitives and by making use of the MetaWare Compiler's ability to automatically generate references to XY memory. The MetaWare Toolkit includes a rich library of DSP functions such as FFT and DCT, FIR and IIR filters, as well as vector and matrix math functions, allowing software engineers to rapidly implement algorithms from standard DSP building blocks.

The toolkit also includes an ITU-T base-ops library for developing voice codecs. For further DSP optimizations, programmers can take advantage of available native fixed-point data types, C++ wrapper classes and an API for fixed-point math primitives. Intrinsics can be used to manually optimize code for maximum performance and power savings.

In addition, the embARC Open Software Platform gives all ARC EM software developers online access to a comprehensive suite of free and open-source software that eases the development of code for IoT and other embedded applications.