The hardened floating point DSP blocks are integrated in Altera’s 20 nm Arria 10 FPGAs and SoCs – currently shipping – as well as 14 nm Stratix 10 FPGAs and SoCs. Integrated hardened floating-point DSP blocks, combined with an advanced high-level tool flow, enable customers to use Altera’s FPGAs and SoCs to address an expanding range of computationally intensive applications, such as high-performance computing (HPC), radar, scientific and medical imaging.

The hardened single-precision floating point DSP blocks included in Arria 10 and Stratix 10 devices are based on Altera’s innovative variable precision DSP architecture. Unlike traditional approaches that implement floating point by using fixed point multipliers and FPGA logic, Altera’s resource efficient, hardened floating point DSP blocks eliminate nearly all the logic usage required for existing FPGA floating-point computations.

This technology enables Altera to deliver up to 1.5 TeraFLOPs (floating point operations per second) DSP performance in Arria 10 devices and up to 10 TeraFLOPs DSP performance in Stratix 10 devices. DSP designers are able to choose either fixed or floating-point modes and the floating point blocks are backwards compatible with existing designs.

“The implementation of IEEE 754-compliant floating-point DSP blocks in our devices is truly a game-changer for FPGAs,” said Alex Grbic, director of software, IP and DSP marketing at Altera.

“With hardened floating point, Altera FPGAs and SoCs offer a performance and power efficiency advantage over microprocessors and GPUs in an expanded range of applications.”