These expansions to the Cadence System Development Suite enable system and semiconductor companies in the mobile, consumer, networking and storage segments to efficiently address important design challenges such as early software bring-up and reduced power consumption.

Built using Xilinx Virtex-7 2000T FPGAs, the Protium platform is Cadence’s second-generation FPGA prototyping platform for software development. It improves productivity by reducing prototype bring-up time by up to 70 percent versus competitive solutions, shortening the process from months to weeks.

Featuring Palladium flow compatibility, a 4X increase in capacity versus the previous generation, and support for up to 100 million gates, the Protium platform enables software development and throughput regressions supported by a fully automatic flow and the capability to execute user-driven performance optimizations.

The Protium platform also provides automated memory compilation, external bulk memory support, and RTL name preservation throughout the flow, which minimizes the tedious and error-prone manual FPGA bring-up steps, thereby speeding up time to market.

“The ability to use the same bring-up flow for Palladium emulation and Protium rapid prototyping, allows our design teams to switch seamlessly between the two execution engines, which reduces the prototype bring-up time from months to weeks compared to traditional FPGA-based prototyping approaches,” said Hideya Sato, deputy executive general manager, Global MONOZUKURI Division, Information & Telecommunication Systems Company, Hitachi, LTD.

“Additionally we expect to improve overall development productivity by extending the use of Protium rapid prototyping platform to the area of hardware/software co-verification.”

“The growing need for software and hardware verification continues to drive the use of FPGA-based ASIC prototyping, from emulation and prototyping to mass production applications,” said Arun Iyengar, vice president, A&D, ISM and TM&E markets for Xilinx. “Cadence’s approach to unify hardware verification using Palladium emulation and software development using Protium prototyping will further streamline the customer’s time to market while improving product quality.”

Low-power analysis and verification is a key part of system and system-on-chip (SoC) signoff criteria. Addressing this, Cadence has expanded the Dynamic Power Analysis in the Palladium XP II platform beyond Common Power Format (CPF) support, adding verification and debug support for the IEEE 1801 standard.

The Cadence System Development Suite now offers an integrated and consistent low-power flow for engineers using either of the power standards across the Incisive formal and simulation and Palladium platforms, with common power plan and metrics, and integrated debug analysis.