Its extraordinary feature set and performance/power/area leadership place the I6400 far ahead of the competition, enabling customers to implement a smaller core at the same performance, or a faster core in the same area.

MIPS Warrior I-class processor cores set a new standard for mainstream 64-bit processing in applications including embedded, mobile, digital consumer, advanced communications, networking and storage—the broadest set of applications ever addressed by a single MIPS core family.

Says Tony King-Smith, EVP marketing, Imagination: “This is the MIPS Warrior core that many have been waiting for. As the industry moves toward instruction set neutrality, customers can now choose a CPU based on its technical superiority.”

“ The I6400 is more efficient, flexible and scalable than the competition, and its feature set clearly lends itself to the needs of a wide range of next-generation applications including smartphones and tablets. We know that unique features like multi-threading provide significant advantages for many applications, and customers already using this technology agree. Unsurprisingly, we’ve already secured licensees for the I6400 across multiple markets.”

Says Jim McGregor, founder and principal analyst, Tirias Research: “To address the ongoing evolution in applications from IoT to mobile to networking and storage, companies need to select scalable platforms that can future-proof their designs.”

“With 64-bit, multi-threading, and multicore/multi-cluster support, the I6400 is designed to be a phenomenally flexible, low-power processor architecture capable of scaling across a wide range of applications. Imagination now has MIPS IP cores for everything from microcontrollers to 64-bit servers, delivering choice across the range and changing the competitive dynamic in the industry.”

The I6400 features the latest generation of the MIPS Coherency Manager fabric based on a new multicore coherent interconnect architecture. It supports multicore configurations of up to six cores per cluster where multiple cores on a single cluster can have different synthesis targets, and operate at different clock frequencies and voltages. The Coherency Manager fabric implements numerous high-performance features including hardware pre-fetching as well as wider buses and lower latencies compared to previous generations.

I6400 cores are designed to be delivered in diverse combinations of threads, cores and clusters, supporting multi-cluster fabric configurations up to 64 clusters. The cores are also designed to operate in heterogeneous clusters in future SoC implementations leveraging CPUs, GPUs and other processing elements.

The new I6400 core family is based on the MIPS Release 6 (r6) architecture, benefiting from the continuing evolution of the MIPS instruction set. Targeting next-generation applications, MIPS r6 features new instructions for enhanced performance on JITs, JavaScript, browsers, PIC (position independent code) for Android, and today’s larger workloads.

As a true superset of the MIPS32 architecture, the MIPS64 architecture doesn’t require separate ISAs, datapaths or mode switching, eliminating wasted silicon area and power. Future MIPS Warrior cores will take advantage of the enhanced MIPS r6 architecture and where appropriate the new generation Coherency Manager fabric.

Features:

－ Highly efficient, scalable 64-bit performance

－ Hardware multi-threading

－ Hardware virtualization

－ Next-generation security

－ Advanced power management

－ Efficient FPU

－ 128-bit SIMD