The expanded partnership grants rights to deliver reference designs and physical design knowledge for integrating ARM Cortex processors, ARM CoreLink system IP, and ARM Artisan physical IP along with RF/analog/mixed-signal IP and embedded flash into the Virtuoso-VDI Mixed-Signal Open Access integrated flow for the new TSMC process technology offerings of 55ULP, 40ULP and 28ULP.

This new collaboration builds on existing multi-year programs to optimize performance, power and area (PPA) via Cadence’s digital, mixed-signal and verification flows and complementary IP alongside ARM Cortex-A processors and ARM POP IP targeting TSMC 40nm, 28nm, and 16nm FinFET process technologies.

Similarly, the companies have been optimizing the solution based around the Cortex-M processors in mixed-signal SoCs targeting TSMC 65/55nm and larger geometry nodes. The joint Cortex-M7 Reference Methodology for TSMC 40LP is the latest example of this collaboration.

“TSMC’s new ULP technology platform is an important development in addressing the IoT’s low-power requirements,” stated Nimish Modi, senior vice president of Marketing and Business Development at Cadence.

“Cadence’s low-power expertise and leadership in mixed-signal design and verification form the most complete solution for implementing IoT applications. These flows, optimized for ARM’s Cortex-M processors including the new Cortex-M7, enable designers to develop and deliver new and creative IoT applications that take maximum advantage of ULP technologies.”

“The reduction in leakage of TSMC’s new ULP technology platform combined with the proven power-efficiency of Cortex-M processors can enable a vast range of devices to operate in ultra energy-constrained environments,” said Richard York, vice president of embedded segment marketing, ARM.

“Our collaboration with Cadence enables designers to continue developing the most innovative IoT devices in the market.”