The new devices are architected to support the higher memory needs of compute-intensive applications such as machine learning, Ethernet connectivity, 8K video, and radar. They also contain CCIX IP, enabling cache-coherent acceleration to any CCIX-enabled processor to address compute acceleration applications.

"In package integration of DRAM represents a massive leap forward in memory bandwidth for high end FPGA-enabled applications," said Kirk Saban, senior director of FPGA and SoC Product Management at Xilinx.

"HBM integration in our industry leading devices provides a clear path to multi-terabit memory bandwidth and our acceleration enhanced technology will enable efficient heterogeneous computing for our customers' most demanding workloads and applications."

Based on the proven 16nm Virtex UltraScale+ FPGA family, which started sampling in 2015, the HBM-optimized Virtex UltraScale+ products offer the lowest-risk approach to HBM integration. The family is built using 3rd generation CoWoS technology—co-developed by TSMC and Xilinx and now the industry standard assembly for HBM integration.