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Synopsys' Foundation IP on TSMC's 40-nm eFlash processes implements unique features that enable designers to reduce power consumption for IoT designs. The logic libraries include multiple channel gate lengths and ultra-low leakage standard cells to minimize leakage power, and offer power optimization kits and multi-bit flip-flops to achieve near-threshold operation down to 60 percent of nominal voltage.
The embedded memories offer light sleep, deep sleep, and shut-down power management features for the lowest leakage, as well as assist circuitry to enable the lowest operating voltages. The DesignWare Logic Library and Embedded Memory IP on the TSMC 40-nm eFlash processes is available through Synopsys' Foundry-Sponsored IP Program, which enables qualified customers to license the IP at no cost from Synopsys.
"TSMC continues to build on our long history of collaboration with Synopsys to deliver high-quality, proven DesignWare IP on a wide range of TSMC processes that help our mutual customers achieve their design objectives," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "The availability of Synopsys' Foundation IP for our 40-nm eFlash processes demonstrates how Synopsys continually invests in developing IP that enables designers to achieve the best power and area for their SoCs."
"Synopsys and TSMC have worked closely together for many years to understand designers' specific performance, power and area requirements for their target applications," said John Koeter, vice president of marketing for IP at Synopsys. "By offering foundry-sponsored DesignWare Logic Library and Embedded Memory IP with differentiated low-power features for TSMC's 40ULP eFlash and 40LP eFlash processes, we are enabling designers to improve energy efficiency and extend battery life of their IoT products."
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