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“Advanced wafer-level packaging technologies hold the key to meeting future technology needs, from mobile devices to automotive applications, to those required for enabling the IoT,” noted Dr. Robert Castellano, [resident of The Information Network. “Flip chip technology is slowly replacing wire bonding for many high-performance chips, and wafer level packaging (WLP) is replacing flip chip.”
To meet the needs of thinner mobile devices, fan-out WLP (FO-WLP) enables redistribution of I/Os beyond the chip footprint, differing from Fan-in WLP in several key areas. One major advantage of FO-WLP, especially in mobile applications, is that the elimination of the substrate reduces the vertical footprint by an average of 40% compared with Fan-in WLP, enabling thinner products or making it possible to stack more components in the same form factor.
The elimination of the interposer and TSVs also provides a cost reduction and eliminates concerns on the effects of TSVs on electrical behavior. The reduced path to the heat sink also helps improve thermal performance.
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