TAIPEI, Taiwan - ASE yesterday announced together with TDK the joint establishment of ASE Embedded Electronics Incorporated...
TAIPEI, Taiwan - Advanced Semiconductor Engineering, Inc. was today recognized by Thomson Reuters as a 2018 Top 100 Global Technology Leader...
The solution consists of the SiP-id (System-in-Package - intelligent design) design kit, an enhanced reference flow including IC packaging and verification tools from Cadence, and a new methodology that aggregates the requirements of wafer-, package- and system-level design into a unified and automated flow. By deploying the SiP-id methodology, designers can reduce design iterations and greatly improve throughput as compared to existing advanced packaging
To provide a more holistic approach to the design and verification of SiP and advanced fan- out packages, ASE and Cadence collaborated closely to develop a design kit, methodology, and streamlined and automated reference flow using enhanced Cadence IC packaging and verification tools, all tailored for ASE’s advanced IC package technologies. In a typical use case with high-pin-count dies, packaging engineers using SiP-id and the accompanying reference flow and methodology were able to reduce time from more than six hours to only 17 minutes, compared to existing tools with manual operation.
“As the leader in System-in-Package technology, ASE has been augmenting our design and manufacturing services by building a SiP ecosystem with partners across the entire supply chain including EDA providers,” said C. P. Hung, vice president, Corporate R&D, ASE Group.
“SiP-id is a prime example of the successful collaboration between ASE and Cadence that achieved optimal results through the mutual sharing of technology and experiences. Ultimately, we aim to offer our customers a set of efficient EDA tools to design more complex chips using ASE’s advanced package and system-level technologies and help them speed up time to market,” he added.
“More and more of our customers are looking at multi-die advanced-package technologies to solve their next- generation design challenges,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “Advanced packaging extends Moore’s Law and plays directly into our System Design Enablement strategy, so collaborating with ASE to fulfill their vision for SiP is a natural fit for us. We expect the results of this effort to mutually benefit Cadence and ASE customers by providing a methodology optimized for SiP design.”
CTIMES loves to interact with the global technology related companies and individuals, you can deliver your products information or share industrial intelligence. Please email us to firstname.lastname@example.org
- 1The Average Contract Prices of Enterprise SSD May Fall by 10% in 2Q18, Says TrendForce
- 2LG Display Retains Its Lead in the Large Displays Shipments in Q1 2018, IHS Markit Says
- 3TrendForce: Three Major Server DRAM Suppliers Score 10.3% Revenue Growth in 1Q18
- 4AUO Announces World’s Highest Resolution Micro LED Display Technology
- 5Asus, Taiwan Mobile, Quanta Collectively Spend NT$1.1B to Establish Taiwan AI Platform