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Intel Start to Ship Its First 10nm Agilex FPGAs
Published: Aug 30,2019Intel today announced that it has begun shipments of the first Intel Agilex FPGAs to early access program customers. Participants in the early access program include Colorado Engineering Inc., Mantaro Networks, Microsoft and Silicom. These customers are using Agilex FPGAs to develop advanced solutions for networking, 5G and accelerated data analytics.
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"The Intel Agilex FPGA product family leverages the breadth of Intel innovation and technology leadership, including architecture, packaging, process technology, developer tools and a fast path to power reduction with eASIC technology. These unmatched assets enable new levels of heterogeneous computing, system integration and processor connectivity and will be the first 10nm FPGA to provide cache-coherent and low latency connectivity to Intel Xeon processors with the upcoming Compute Express Link." said Dan McNamara, Intel senior vice president and general manager of the Networking and Custom Logic Group.
In the data-centric, 5G-fueled era, networking throughput must increase, and latency must decrease. Intel Agilex FPGAs provide the flexibility and agility required to meet these challenges by delivering significant gains in performance and inherent low latency.
Reconfigurable and with reduced power consumption, Intel Agilex FPGAs have computation and high-speed interfacing capabilities that enable the creation of smarter, higher bandwidth networks and help deliver real-time actionable insights via accelerated artificial intelligence (AI) and other analytics performed at the edge, in the cloud and throughout the network.
The Intel Agilex family combines several innovative Intel technologies including the second-generation HyperFlex FPGA fabric built on Intel's 10nm process, and heterogeneous 3D silicon-in-package (SiP) technology based on Intel's proven embedded multi-die interconnect bridge (EMIB) technology.
This combination of advanced technologies allows Intel to integrate analog, memory, custom computing, custom I/O and Intel eASIC device tiles into a single package along with the FPGA fabric.
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