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Wafer Capacity by Feature Size Shows Rapid Growth at <10nm

Published: Oct 17,2019

Leading-edge processes (<28nm) took over as the largest portion in terms of monthly installed capacity available in 2015. By the end of 2019, <28nm capacity is forecast to represent about 49% of the IC industry’s total capacity, based on information in IC Insights’ Global Wafer Capacity 2019-2023 report.

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At the very leading edge, <10nm processes are now in volume production and are forecast to represent 5% of worldwide capacity in 2019. The share of <10nm capacity is forecast to jump to 25% and become the largest capacity segment by 2023.

South Korea (Samsung) and Taiwan (TSMC) are currently the only two regions with fabs processing what are being called <10nm processes. South Korea and Japan both have large shares of capacity in the <20nm – ≥10nm segment, with the vast majority of it being used to produce NAND flash (equivalent feature size) and DRAM, but also some for advanced logic and application processors built with 14nm, 10nm, or 8/7nm technology. Taiwan also has a large share of the <20nm – ≥10nm capacity, with roughly half of it being for foundry services and the other half for DRAM production.

Trends at the leading edge have been changing and the industry is departing from historical “norms.” The gray area of what constitutes a generation and how to measure the minimum process geometry gets more difficult every year. Therefore, any assumptions made regarding the wafer fab capacity of new process technologies can have a big impact on the forecast for wafer capacity by minimum feature size.

Taiwan has the largest shares of capacity in the <65nm – ≥28nm and <0.2µ – ≥65nm technology segments. Nevertheless, the 28nm, 45/40nm, and 65nm generations continue to generate significant business volumes for foundries like TSMC and UMC.

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