The AD9554 dissipates only 940 mW of power while generating up to eight output clocks over an output range of 430 kHz to 941 MHz, synchronized to four 2-kHz to 1-GHz external input references, with a loop bandwidth as low as 0.1 Hz. The four analog-digital phase-locked loops (ADPLL) enable the reduction of input jitter or phase noise associated with the external references.

The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low jitter output clock even when all reference inputs have failed. The AD9554 has adaptive clocking capability that allows the user to dynamically change the DPLL divide ratios while they are locked.

The AD9554 clock’s high level of integration, adaptive clocking capability, and OTN mapping algorithm embedded in DPLL, can reduce system costs by simplifying clocking circuitry and eliminating software control routines. Output jitter is 250 fs over the 50-kHz to 80–MHz range and 350 fs over the 12-kHz to 20-MHz range.

Features:

－ GR-1244 Stratum 3 stability in holdover mode

－ Smooth reference switchover with virtually no disturbance on output phase

－ Adaptive clocking allows dynamic adjustment of feedback dividers in OTN mapping/demapping

－ Quad ADPLL architecture:Four reference inputs (single-ended or differential)/Eight outputs (single-ended or differential)

－ 4x4 crosspoint allows any reference input to drive any output

－ Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261, and ITU-T G.8262

－ Loop bandwidth as low as 0.1Hz to guarantee SyncE compliance