The Broadcom StrataDNX products are the world's first to provide 800 Gbps packet processing per device at a high interface bandwidth while integrating a scalable multi-terabit switch fabric, hierarchical traffic manager, external packet buffer memory and advanced packet processing. This unique combination enables equipment makers to deliver network equipment with a higher port density, lower power consumption and greater subscriber scale in a smaller physical system size.

The StrataDNX family of expandable products is complementary to Broadcom's highly integrated StrataXGS Trident and Tomahawk SoCs. Together they provide the industry's most comprehensive end-to-end portfolio of switching solutions across the carrier, data center and enterprise markets.

"With the addition of our latest StrataDNX products to our switch portfolio, Broadcom is delivering the most comprehensive switching platform in the industry," said Ram Velaga, Broadcom Senior Vice President and General Manager, Network Switch. "These devices will change the way customers build and deploy networking equipment by providing a unique combination of advanced core features at a level of high bandwidth integration never before possible."

The StrataDNX family supports pre-standard implementation for 25 and 50 Gigabit Ethernet, enabling direct connectivity to the Broadcom BCM56960 Tomahawk switch SoC, the industry's first high- density 25/100 Gigabit Ethernet switch for cloud-scale networks. In addition, the devices support port speeds of up to 400 Gbps, enabling the world's largest interconnect pipes and roadmap to 400 Gigabit Ethernet. Integrated accelerators for carrier service management provide visibility and control for carrier networks and distributed data centers traversing a wide area network (WAN).

Broadcom's StrataDNX line delivers a complete set of advanced features for the most demanding carrier, campus and cloud environments. The devices support external DRAM-based packet memory offering up to 300x more traffic buffering compared with on-chip memory, enabling zero-packet-loss in heavily congested networks. In-field reconfigurable flexible packet processing engines allow for customer-specific forwarding paradigms or future support of new and emerging protocols.

On-chip hierarchical traffic management ensures per-subscriber bandwidth guarantees, required by carrier networks to deliver on service level agreements (SLAs). For optical transport applications, the architecture enables converged carrier Ethernet and optical transport network (OTN) traffic over a unified fabric, enabling significant savings in carrier CapEx and OpEx.