“As a PCI-SIG member for more than 10 years, Cadence holds a valued role in the success of PCIe technology,” said Al Yanes, president and chairman of PCI-SIG. “By participating in the compliance program, Cadence is helping to ensure the continued adoption of the PCIe architecture.”

The Cadence PHY IP for PCIe 3.0 technology is a low power solution, enabling customers to implement a PCIe 3.0x16 solution with power consumption under 1W. It also enables seamless SoC integration by allowing customers to prototype their design and test compatibility with other PCIe devices. The FPGA platform for evaluation and product development offered with the solution supports the 8GT/s data rate specified under PCIe 3.0 requirements.

“With the lowest power consumption in the market, our certified solution enables customers to build extremely power-efficient designs,” said Gary Dick, PCIe architect, IP Group at Cadence. “With the FPGA platform, our customers can fully test and emulate application logic before the design is implemented.”

“As part of its successful PCIe compliance testing, Cadence utilized the leading-edge PCIe 3.0 test and development tools from Teledyne LeCroy,” said John Wiedemeier, product marketing manager at Teledyne LeCroy.

“This is the latest example of many years of partnership between the two companies on comprehensive compliance testing that enable designers to confidently integrate high-speed PCIe interfaces into their SoCs.”