Taipei, Sunday, Nov 24, 2024, 15:51

News

Imec and sureCore Collaborate on SRAM Design IP

Published: Mar 31,2015

sureCore Ltd., the low power SRAM IP company and nanoelectronics R&D center imec today announced that they are collaborating on low-power SRAM IP. The collaboration includes the licensing of a set of imec SRAM design IP to sureCore to expand sureCore’s IP portfolio and a participation in sureCore. Moreover, sureCore will establish a branch in Leuven to tap into the design ecosystem around imec.

More on This

Imec’s Virtual Fab Underpins Strategies to Reduce the Carbon Footprint of Lithography and Etch

At the 2023 Advanced Lithography + Patterning Conference, imec presents a quantitative assessment of the environmental impact of patterning in advanced IC manufacturing...

Swave, a new Imec and VUB Spin-off, Raises €7M to Deliver True AR/VR Experiences

Swave Photonics, an innovator in Holographic eXtended Reality (HXR) technology to bring the metaverse to life, today announced a €7 million seed round...

“This collaboration is strategically very significant for us,” explained Paul Wells, sureCore’s CEO. “This will enable expertise to be pooled and shared to drive forward the development of low power SRAM IP solutions. Imec has world renowned silicon process expertise and an extensive IP portfolio that we will access.”

“We are convinced of the effectiveness of sureCore’s SRAM IP technology to solve the power issues of next generation wearable electronics and Internet of Things (IoT) applications where extending battery life is crucial. It is also valuable in the networking space where power and heat dissipation are critical considerations,” added Ludo Deferm, Executive Vice President Corporate, Business and Public Affairs at imec.

“By licensing a number of our ultra-low power design technology patents to sureCore, we aim at supporting sureCore to further improve the power efficiency of their SRAM IP blocks.”

Guillaume d’Eyssautier, sureCore’s Chairman, commented, “sureCore has identified the window of opportunity for SRAM IP that offers compelling lower power performance of more than 50% savings. This is caused by the discontinuity in Moore’s Law that means that 1 million transistors will cost more and consume more power at 20nm than at 28nm. ”

“As a result, for many applications, 40/28nm bulk CMOS as well as 28nm FDSOI, will be cost effective for a long time, and being able to cut power consumption with better SRAM IP will make a significant commercial difference. We have run a successful 28nm test chip in March last year that delivered more than 50% power savings versus industry-standard SRAMs,” Guillaume said.

CTIMES loves to interact with the global technology related companies and individuals, you can deliver your products information or share industrial intelligence. Please email us to en@ctimes.com.tw

842 viewed

comments powered by Disqus