“We are pleased with our choice of the Andes N9 CPU core for our next SoC design,” said Richard Terrill, Vice President of Marketing at Wave Semiconductor.

“We needed a small but powerful CPU to manage critical tasks at power-up boot and on-going observation of chip operation. The N9’s programming tools and support of the AXI bus interface fit our requirements nicely. Its straightforward synthesis made for integration into our larger design and its small silicon footprint provided an added bonus.”

“Andes is thrilled that Wave Semiconductor chose our N9 CPU core for their new SoC design,” said Frankwell Lin, President of Andes Technology Corporation.

“The N9 delivers high performance in a small gate count and on a low power budget. Its ability to provide low-latency vectored interrupt makes it very efficient for high performance real time monitoring. The N9’s ability to mix 16- and 32-bit instruction format enables compact code and the five-stage clock-gated pipeline contributes to the core’s 3.43 CoreMark/MHz performance, while its power management instructions conserve power.”