Taipei, Friday, Aug 18, 2017, 16:46

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GUC Successfully Rolls out HBM2 Total Solution

Published: Jun 19,2017

HISNCHU, Taiwan – Global Unichip, the custom ASIC company, has successful taped out a 16nm, second-generation High Bandwidth Memory (HBM) PHY and controller with verified interposer design and CoWoS Package. The innovative ultra-high capacity memory ASIC solution will meet the demanding requirements of artificial intelligence (AI), deep learning (DL), and a variety of high performance computing (HPC) applications.

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“The research and development of HBM using 3D memory technology has been quite stunning. This tape out is especially significant because, for the first time, it integrates new HBM PHY/Controller IP into an SoC and accesses stacked memory die through a GUC-designed interposer and bundled into a chip-on-wafer-substrate (CoWoS) 2.5D package. We are looking forward that the high speed, low-power 256GB/s HBM IP will offer unprecedented DRAM performance and allow faster responsiveness for high-end computing tasks.” said C.J Liang, Senior VP of R&D of GUC.

High bandwidth memory (HBM) is a high-performance RAM interface for 3D-stacked DRAM. It is normally used in conjunction with high-performance graphics accelerators and network devices. It adopted by JEDEC as an industry standard in October 2013 and the second generation, HBM2, was accepted by JEDEC in January 2016.

HBM2 is the next generation memory protocol for SoC designs, achieving 2Gb/s per pin, maximum 1024 pins, total bandwidth 256GB/s. The 1024-pin HBM2 PHY connects with an eight-high DDR memory die stack using a through-silicon via. This configuration required adoption of TSMC's CoWoS (Chip On Wafer On Substrate) advanced 2.5D packaging technology. CoWoS integrates multiple chips into a single package using a sub-micron scale silicon interface (interposer) that enables higher performance, lower power consumption, and smaller form factor.

GUC created both the interposer and substrate design, managed the entire package construction, and designed the HBM2 PHY and controller IP to be compliant with JESD235A specification. The company successfully uses CoWoS Technology to integrate GUC SoC, interposer and package design, HBM2 chip, TSMC interposer and CoWoS process to validate GUC HBM PHY, Interposer design, CoWoS DFT, Package and Test solution.

"The complexity of this task is clearly enormous. It demonstrates both the collaboration and technical skills required to take on the high performance computing challenges that are at the foundation of many future innovations," explained Ken Chen, President of GUC.

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