This optimized M1+ library supports the essential multi-track cells (7T/9T/12T), multi-Vt cells (LVT/RVT/HVT), and Faraday low-power PowerSlash kit to build the best portfolio of power, performance, and area metrics which are critical to optimizing digital design implementations targeted at diverse market applications.

Taking full advantage of its ASIC implementation and library development experience, Faraday M1+ library can leverage the routing resources for customer designs to optimize area, and routing time. Comparing to other libraries, the M1+ Library has yielded a 14% reduction of silicon area, with a 43% decrease in leakage power consumption, while maintaining the same performance for digital IPs such as ARM cores and the high-end video codecs. As the results, it helps satisfy customer demands on low-power, high-density, and high-speed applications.

“Library vendors usually focus on small cell size and maximum cell counts per square millimeter, which might cause long routing time and unwilling routing results,” said Flash Lin, Chief Operating Officer of Faraday. “Faraday has a solid understanding of how library routability plays a vital role in SoC designs at advanced nodes. We continue to invest in our libraries and our design methodologies to ensure that our customers have what they need to produce highly optimized solutions at the most cost-effective way.”