Faraday’s FPGA-to-ASIC conversion service, in conjunction with comprehensive IP solutions of PCIe Gen 3/4, MIPI D-PHY, DDR3/4 and SerDes 12/16/25/28/56G at advance FinFET process nodes, are particularly suited for AI chips requiring higher bandwidth and a lower latency interface. From cloud to edge computing, in applications like machine vision, NLP, and sentiment analysis, Faraday can deliver optimized ASIC chip designs featuring 30~100 times better energy efficiency.

With 25 years of IP development experience, Faraday has the ability to customize IPs for ASIC cost efficiency in mass production. Faraday has handcrafted SRAM macros allowing for a reduction of on-chip SRAM area by 5~50%, in addition, its SRAM Redundancy & Repair design feature increases yield rates by up to 10%.

“As AI algorithm mature and the market demand for AI products rise, customers look to replace FPGA chips with ASIC devices for a competitive system BOM cost. Faraday’s ASIC service has been validated in thousands of designs and shipped hundred millions of market proven SoCs. The service provides AI customers with a path to lower integration risk and cost, accelerating the adoption of new DNN algorithms”, said Flash Lin, COO of Faraday Technology.