NeoFuse, eMemory’s secure OTP solution, has been taped out for TSMC’s 16nm FF+/FFC, 12nm and 7nm processes with the 16nm FF+/FFC IP qualified and designed-in for applications requiring content protection, including digital TV, set-top box, etc.

The IP is scheduled to tape out with security-enhanced features for TSMC’s 7nm process in the second quarter of this year. The enhanced solution combines the NeoFuse macro with eMemory’s security IP NeoPUF, providing a fundamental protection against data breaches and chip counterfeiting.

In the wake of a series of recent cyberattacks, there has been a growing demand for chip security implemented early in both design and manufacturing. eMemory’s NeoPUF is a chip security technology originated from silicon physical uncloneable functions and tailored for a range of applications including AIoT(AI+IoT) and automotive.

The enhanced NeoFuse on TSMC’s 7nm process provides a silicon-embedded chip identifier and a random source for crypto applications, on top of secure storage of sensitive data.

eMemory and TSMC have collaborated closely for many generations of the foundry’s processes. The company’s IP solutions have been taped out on more than 65 TSMC process platforms for a broad range of applications, including display driver IC, PMIC, Controller, IoT related IC, sensor, automotive, etc.

“eMemory has been a close partner of TSMC and our collaboration consistently drives technology innovation and enables advanced SoC designs,” said Suk Lee, Senior Director, Design Infrastructure Marketing Division at TSMC. “We’re looking forward to working with eMemory to continue the pursuit of innovation.”

“As TSMC’s process technologies evolve rapidly, so does eMemory’s IP development,” said Michael Ho, Vice President of Business Development at eMemory. “The breadth and depth of our IP offerings ensure that customers consistently have what they need to enable their designs and accelerate time to market.”

The enhanced NeoFuse on TSMC’s 7nm process provides a 4K*32 bit OTP Macro and supports the AECQ100 Grade 0 temperature standard (-40 to 150°C). The NeoPUF IP provides a large entropy source up to 4K bits and achieves zero failure rate without the use of the helper data.

The NeoFuse solution has also been taped out for TSMC’s 22nm ULP process and the security-enhanced version is scheduled to tape out for 22nm ULL process in June 2018.