The newly launched USB IP, the smallest in its class, comes with both I2C and APB interfaces for register setting, which can facilitate IP controllability after being integrated into a SoC design; it also reduces the testing cost for mass-production by supporting loopback test mode on the differential IOs.

“Faraday’s USB 2.0 OTG PHY is a cost-effective, feature-rich solution with industry leading silicon area. In addition, Faraday provides a PHY daughter board for system-level FPGA development and verification; the subsystem of PHY and controller is also offered to reduce the engineering effort required for system integration,” said Flash Lin, Chief Operating Officer of Faraday. “This USB 2.0 IP with the same tiny architecture is currently in validation phase on UMC 28nm process nodes and will be available later this year.”