Faraday’s SerDes IP is designed with a system-level approach to provide outstanding metrics across power, performance and area. By adopting the programmable architecture that covers data transfer rates up to 28Gbps, this SerDes IP can readily support the optimization of SoC chip designs from 100Gbps of throughput. On top of that, the IP supports multiple interface standard protocols, such as OIF-CEI, JESD, PCIe Gen1-4, and Ethernet.

“28G SerDes PHY technology has become a crucial building block in addressing a broad range of wired and wireless communication applications,” said Flash Lin, Chief Operating Officer of Faraday.

“Faraday's latest 28nm SerDes solution can meet 25/28G SerDes requirements with lower NRE (non-recurring engineering) expense and lower cost compared with other FinFET-based 28G SerDes solutions. By leveraging this solution, we are ready to engage with ASIC customers to reach their potential needs in high-growth networking markets.”