IC Compiler II has been in production usage since July 2014 and has being actively employed for tapeouts by several semiconductor companies across a range of process technology nodes. This latest release introduces additional key technologies including multi-objective concurrent clock and data optimization, advanced low power optimization techniques and early support for 10-nm process technology. With immediate availability of the IC Compiler II 2014.12 release, Synopsys brings the Power of 10X to the broader physical design community.

"Having worked closely with Synopsys since the early days of the IC Compiler II, we have been eagerly anticipating the 2014.12 release," said Tatsuji Kagatani, department manager of Design Automation Department, Elemental Technology Development Division 1 at Renesas System Design Co., Ltd.

"IC Compiler II delivered truly impressive turnaround time as well as good QoR (quality of results) during the design activities of our latest micro-controller-unit (MCU) design in 40-nanometer technology this year. We have come to view IC Compiler II as a key enabler of competitive differentiation, and are in the process of extending its application to all key in-flight programs across 40 nanometers to 28 nanometers and below technology nodes."

IC Compiler II is a full-featured, production-ready netlist-to-GDSII implementation system delivering the highest throughput and productivity along with the best quality of results. Developed from the ground-up to deliver a leap forward in productivity, IC Compiler II is built on a new highly efficient multi-everything infrastructure and offers ultra-high capacity design planning, unique new clock-building technology and advanced global analytical closure techniques.

These technologies enable IC Compiler II to deliver a 5X speed-up in implementation runtime with half the memory and half the iterations required to achieve target performance. Together, this enables a 10X boost in design throughput. Early users of IC Compiler II have observed even greater speed-up in the design planning stages where the speed of execution is a key enabler of exploration, helping arrive at the best possible floorplan for detailed implementation.

This level of speed-up is enabling game-changing possibilities for users of IC Compiler II, with some electing to coalesce several partitions in one large partition and thus gain higher efficiency, and others electing to aggressively fine-tune to drive higher device performance. Still others are electing to compress their overall development cycles and reach tapeout sooner.

The 2014.12 release of IC Compiler II enables an even richer feature-set targeting established as well as emerging node technology. New capabilities include new multi-objective concurrent clock and data for pre and post route optimization, advanced low power optimization techniques, electro-migration (EM) analysis, transparent interface optimization (TIO) and support for 10-nm process technology.

"Since our announcement of IC Compiler II earlier this year, customer response has been extremely positive, and the demand to gain access has been unprecedented. With broad availability of the 2014.12 release, we are well positioned to meet this growing demand," said Antun Domic, executive vice president and general manager of the Design Group at Synopsys.

"IC Compiler II is a landmark achievement that has been in the works for several years and is made possible by an asset mix unique to Synopsys – a deep and talented resource pool, diverse customer feedback by virtue of market leadership, and the ability to closely collaborate with some of the best, most advanced designers in the world."