In a previously published article, [1], the impact of parasitics on performance was discussed. The eGaN FET outperformed lower voltage

rated MOSFETs by combining low figure of merit, low package parasitics, and low loop inductance. For the eGaN FET, the PCB layout domi

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nated the parasitics when employing a conventional PCB Layout. This white paper will explore the optimization of PCB layout for an eGaN

FET based point of load (POL) buck converter, comparing the conventional designs and proposing a new optimal layout to further reduce parasitics.

The optimal layout will provide improved efficiency, faster switching speeds, and reduced device voltage overshoot compared to conventional designs.

The eGaN FET based POL buck converters operate at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A.