The reliability of NeoFuse silicon IP can meet the criteria of AEC-Q100 Grade 1 and the design of NeoFuse silicon IP completely changes the traditional dual-voltage operation by using core device only to access data under single low-voltage.

With the soaring demand of automotive ICs from the advent of smart cars and internet of vehicles, the IC suppliers in the increasingly crowded automotive IC marketplace pay attention to not only rigorous reliability requirements but also manufacturing cost.

The process for source driver IC in automotive display panels has gradually migrated from a triple-device process (e.g. 1.8V/3.3V/13.5V) to a dual-device one (e.g. 1.8V/13.5V) to reduce wafer manufacturing cost by simplifying the process steps.

However, the removal of medium voltage device frequently used in silicon IP design leads to the problems of significantly increasing the IP area and the read operation not fulfilling the product requirements.

eMemory’s NeoFuse silicon IP can be implemented by using only core device to perform memory and peripheral circuit design. Its unique circuit design prevents high-voltage damage to the core device during data programming, and only single low-voltage is required to access data in read operation.

Take the NeoFuse Silicon IP in 0.18um 1.8V/13.5V for source driver IC as an example, the core device can sustain 9V high-voltage stress during programming, while a 1.0V low-voltage is needed for read operation.

This innovation completely changed the traditional dual-voltage operating and has been highly valued and adopted by automotive panel driver IC customers.