The features such as low supply voltage operation, compact IP area, and an internal charge pumping circuit are expected to facilitate flexible circuit design, enhance chip integration, and optimize power efficiency in battery-operated devices and IoT-related applications. These unique features also create a secure environment for connected devices in which NeoFuse IP offers the functionality of security key setting and random seed generation.

The enhanced version of NeoFuse IP in the 55nm ULP process will support 0.9V ultra-low voltage operation, and this paves the way for early readiness for data and setting in chip operation.

Moreover, this solution is able to embed the charge pumping circuit to write data in programming mode with insignificant area extension, thus no need to consider high voltage supply, will enable IC design teams to simplify the adoption of embedded NVM solutions and shorten the time to market.

Chris Lu, eMemory Vice President of OTP Business Group, says, “In addition to low power consumption, more and more IP users who are interested in ULP process platforms request low supply voltage operation and compact IP area with simple power supply.

That’s why eMemory is offering the enhanced version of NeoFuse IP in the 55nm ULP process, a NeoFuse-qualified platform, to expand the usage of eMemory’s solution. The enhanced version will be rolled out on other ULP process platforms successively.”

To fulfill the requirements for the devices in IoT related applications, the demands for embedded logic NVM solutions in ULP process nodes is moving towards a wider voltage range and more built-in functions with smaller IP area. Targeting these market requirements, eMemory will offer more platforms for enhanced versions of NeoFuse IP in IoT-related applications.