TAIPEI, Taiwan - Leading up to the RIC-V forum, RISC-V CON, which will be held in Hsinchu on May 9, Andes Technology Cor...
HSINCHU, Taiwan – Andes Technology announced it achieved a record number of design wins for its new family of RISC-V processors during 2018...
Andes is a 12-year-old CPU IP vendor with solutions serving in excess of 2-Billion SoCs covering a wide range of applications. As a natural evolution, Andes has adoped RISC-V as the subset of its fifth generation architecture, the AndeStar V5, and brings it to the RISC-V community. Based on the V5 architecture, Andes announced two high-performance 1+ GHz AndesCore processor IP’s, the 32-bit N25 and the 64-bit NX25, both delivering over 2.8 DMIPS/MHz and over 3.4 CoreMark/MHz, and gate count as small as 30K and 50K, respectively, when using TSMC 28nm HPC process. The N25 and NX25 are ideal for high-speed control tasks in networking, storage, and AI applications.
“To support the ever-increasing features of the emerging applications, SoC engineers face the challenges of the design complexity and time-to-market. They need powerful development tools such as fast system simulation for architectural exploration and SW development, emulation for functional verification and system validation, performance optimization, tough bugs tracing and embedded analytics. That is why Andes has worked with some of the partners on V3 AndesCore processors for many years,” Frankwell Jyh-Ming Lin, President of Andes Technology, commented, “We are now collaborating with Imperas, Lauterbach, Mentor, and UltraSoC to provide those advanced development tools for our new V5 AndesCore N25 and NX25, and the RISC-V community. We are excited to enrich the ecosystem of RISC-V with our partners’ great support, and look forward to the creative products from our common customers in the near future.”
"Imperas supports Andes with Open Virtual Platforms (OVP) Fast Processor Models of the AndeStar V5 processors and with virtual platform- based tools to help with the development, porting, debug and test of software and operating systems running on the V5 processors. Building on our partnership with Andes, Imperas is pleased to deliver our next-generation models, Extendable Platform Kits (EPKs) and software development solutions for the emergent RISC-V ecosystem, to help accelerate their adoption." said Simon Davidmann, CEO of Imperas.
Norbert Weiss, international sales and marketing manager and head of marketing at Lauterbach commented: “For many years, Lauterbach TRACE32 has supported AndeStar V3 architecture and cores. We are happy to continuously support the new V5 processors, N25 and NX25, RISC-V based with enhanced extension architecture. With TRACE32, the developers who are creating products around Andes new V5 processors have access to a full range of debug functionality, from bootstrap code to interrupt routines and drivers. ”
“Mentor’s work with Andes means that mutual customers are assured that the best emulation platform support is available for the Andes’ N25 and NX25 processor IP’s,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “Our support for the V5 AndesCore processors, on the Veloce emulation platform, helps streamline and simplify the design and creation of SoCs based on the N25 and NX25.”
“UltraSoC is committed to increasing the number of silicon design starts, and our participation in Andes V5 processors,” said Rupert Baines, CEO of UltraSoC, “We are committed to supporting the adoption of RISC-V throughout the semiconductor industry, both through our membership in the RISC-V Foundation and via individual partnerships. Making UltraSoC’s on-chip trace and debug IP available through Andes V5 processors will enable chipmakers everywhere to leverage the benefits of open source hardware and introduces new innovative designs to the market.”
Andes, the first mainstream CPU IP vendor to adopt RISC-V instruction set architecture, has been actively contributing for GNU and LLVM toolchains since it joined the RISC-V Foundation. The V5 NX25 and N25 processors are fast and small 5-pipeline CPU IPs with abundant extension features based on feedback from customer interactions over the past 12 years. Andes is committed to driving the acceleration of the acceptance of the RISC-V with our partners.
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