To produce this test chip, imec and Cadence optimized design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence Innovus Implementation System.

Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.

The Innovus Implementation System is a next-generation physical implementation solution that enables system-on-chip (SoC) developers to deliver designs with best-in-class PPA while accelerating time to market. Driven by a massively parallel architecture with breakthrough optimization technologies, the Innovus Implementation System provides typically 10 to 20 percent better PPA and up to 10X full-flow speedup and capacity gain.

“Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries including 5nm and below,” said An Steegen, senior vice president of Process Technology at imec. “Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip. The Cadence next-generation platform is easy to use, which helps our engineering team stay productive in developing the rule set for advanced nodes.”

“By achieving this milestone, Cadence and imec continue to demonstrate our dedication toward pushing patterning technologies to increasingly smaller nodes,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “With imec technology and the Cadence Innovus Implementation System, we’ve created a working flow that can pave the way for developing innovative next-generation mobile and computer advanced-node designs.”